Projects / JTAG (Boundary scan) Test

JTAG (Boundary scan) Test

JTAGTest is an IEEE 1149.1 JTAG Boundary scan tester for embedded designers, production houses, and service companies. It provides a significant aid for PCB debugging, prototyping, testing, and repairing. Using an IEEE 1149.1 (JTAG) boundary-scan, the device pin signals or internal signals can be monitored in real-time without interfering with normal device operation, and you can change pin state manually. It runs under Wine on 32-bit Linux distributions using special Linux support libraries, which are included in the distribution.


Recent releases

  •  01 Jun 2009 14:53

    Release Notes: IEEE JAM/STAPL support, an improved SVF player (with bulk IO and "blind" mode), Lattice SVF extensions (LOOP/ENDLOOP statement), and Xilinx XSVF support.

    •  25 Feb 2009 01:04

      Release Notes: This release adds a ViaTAP JTAG-USB driver bugfix, an improved BGA chip view under Linux, and a modified installer.

      •  14 Feb 2009 11:43

        Release Notes: Initial Linux support (32-bit distributions only).


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