Projects / AsipIDE


AsipIDE is a graphical design front-end able to control any existing compilation, simulation, or synthesis tool to form complete design flows. In addition to providing hierarchical and multi-abstraction design entry, input files can be generated or converted to the required formats, co-simulation is possible, and output files such as trace files can be analysed for debugging within the graphical environment. The framework also encourages an iterative design style where modules are iteratively refined from high-level software simulation to hardware circuits. It is based on the following key ideas: allowing components at any level of abstraction and any description languages to be simulated seamlessly together, with an automatic generation of the co-simulation interfaces; being an extensible platform allowing the integration of any existing tools (open-source tools, in particular, can be brought together as complete tool flows); the ability for networks on chip to be graphically designed, inspected, and optimized; and guiding users in the design of GALS systems by automating the suggestion and placement of GALS adapters and by making debugging and optimizations through simulation easier thanks to advanced visualization techniques.

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